Various circuit layouts have been devised for random access memories (RAM) including static random access memories (SRAM). Moreover, various attempts have been made to design memory circuits that support higher memory bandwidths, that is, higher memory throughput or speed, while attempting to avoid the necessity of increasing the surface area of the circuit layout, also called an area penalty. One type of conventional scheme to increase the memory bandwidth, for example, is called double pumping, that is, to run the memory array at twice the frequency of the core frequency, that is, the clock rate of the processor with which the memory array operates. Even with double pumping, however, the speed of memory access typically limits the maximum core frequency. Another type of conventional scheme to increase the memory bandwidth is to partition a memory into multiple small banks by memory address. If there is no address conflict, multiple banks of memory may be accessed at the same time. A partitioned memory with a structure of multiple small banks, however, may incur an area penalty because such a memory may require a larger surface area than a non-partitioned memory of the same transistor size and the same capacity.
Moreover, various conventional circuits have been designed for SRAM cells with tradeoffs between memory speed, circuit area and the number of read/write ports for memory access. For example, a conventional low-swing 6T memory cell (the number before “T” designates the number of transistors per cell) with a single wordline driver may occupy a relatively small circuit area, but may be only capable of supporting either one read or one write at a given time, and the speed of memory access may be relatively slow. As another example, a conventional full-swing 8T memory cell with separate read and write wordline drivers may be capable of supporting one read and one write at a time for different entries and operating at a relatively fast memory speed. However, such a conventional full-swing 8T memory cell may require an increased circuit area compared to low-speed memory circuits.
Another example of a conventional 8T memory cell design is a low-swing 8T memory cell with shared read/write bitlines that may be capable of supporting two reads, or one write and one read, or two writes at a time for different entries. Although such a conventional low-swing 8T memory cell may be capable of supporting multiple simultaneous reads/writes, it may have a relatively slow memory speed while incurring a relatively large circuit area penalty. Yet another example of a conventional memory cell design is a full-swing 10T memory cell having separate read/write bitlines that may be capable of supporting as many as two reads and one write at a time for different entries and operating at a relatively fast memory speed. However, such a conventional full-swing 10T memory cell typically occupies a significantly larger circuit area than conventional 6T or 8T memory cells. It is typically difficult to satisfy the competing demands of fast memory speed, small circuit size and simultaneous multiple read/write operations in a single memory circuit design.